Kevin Tien, David Frank, et al.
ISSCC 2026
A 28nm SoC solution with integrated proactive power management for droop mitigation is demonstrated combining a neural droop management unit, integrated high speed power converter, and an online learning engine to combat the PDN and workload variations. The 28nm test chip integrated with CPU and accelerators achieves 59% worst-case droop reduction, 48× throttling reduction, and >91% regulator peak efficiency, reducing performance degradation from prior fixed-model or throttling-only schemes.
Kevin Tien, David Frank, et al.
ISSCC 2026
Hazar Yueksel, Ramon Bertran, et al.
MLSys 2020
Matt Cohen, Monodeep Kar, et al.
ISSCC 2026
Laura Bégon-Lours, Mattia Halter, et al.
MRS Spring Meeting 2023