Optimal buffered routing path constructions for single and multiple clock domain systems

Shrinking process geometries and the increasing use of IP components in SoC designs give rise to new problems in routing and buffer insertion. A particular concern is that cross-chip routing will require multiple clock cycles. Another is the integration of independently clocked components. This paper explores simultaneous routing and buffer insertion in the context of single and multiple clock domains. We present optimal and efficient polynomial algorithms that can be used to estimate communication over-head for interconnect and resource planning in single and multi-clock domain systems. Experimental results verify the correctness and practicality of our approach.