On the power of logic resynthesis

A linear arrangement problem, called the minmax mincut problem, emerging from circuit design is investigated. Its input is a series-parallel directed hypergraph (SPDH), and the output is a linear arrangement (and a layout). The primary objective is to minimize the longest path, and the secondary objective is to minimize the cutwidth. It is shown that cutwidth D, subject to longest path minimization, is affected by two terms: pattern number k and balancing number m. Also, k and m are both lower bounds on the cutwidth. An algorithm, running in linear time, produces layouts with cutwidths D ≤ 2(k + m). There exist examples with k = Ω(N), where N is the number of vertices; however, m is always O(log N). We show that every SPDH, after local logic resynthesis (specifically, after reordering the serial paths), can be linearly placed with cutwidth D = O(log N). Simultaneously, its dual SPDH can be linearly placed with the same vertex order and with cutwidth D = O(log N). Therefore, after local resynthesis the area can be reduced by a factor of N/log N. Application to gate-matrix layout style is demonstrated.