Conference paper
I/O buffer placement methodology for ASICs
Joseph N. Kozhya, Sani R. Nassif, et al.
ICECS 2001
Power grids for sub-micron large integrated circuits are performance limiting factors due to the large power dissipated (e.g. 100 W at 1.8 V). The analysis of such power grids is important in order to predict and possibly improve the performance. Current classical analysis methods are falling behind as grids become ever larger. This paper proposes a new efficient analysis method suitable for both DC and transient simulation of large power grids.
Joseph N. Kozhya, Sani R. Nassif, et al.
ICECS 2001
Haifeng Qian, Sani R. Nassif, et al.
DAC 2003
Emrah Acar, Lawrence T. Pileggi, et al.
DATE 2002
Sani R. Nassif
ISQED 2000