Machine intelligence through 3D waferscale integration
Arvind Kumar, Winfried W. Wilcke
S3S 2017
In this paper, we report a lowerature wafer-to-wafer fusion bonding process whose maximum processing temperature is 300C and can potentially be further reduced to 250C. This lowerature process would enhance the compatibility of the three-dimensional wafer-scale integration technology with the devices and with the temporary adhesive materials that might suffer from higherature FBEOL processes. Preliminary experiments are done with blanket 300mm wafers, and characterization results from SAM imaging and mechanical shear test are reported to evaluate the feasibility of the lowerature fusion bonding process.
Arvind Kumar, Winfried W. Wilcke
S3S 2017
Katsuyuki Sakuma, Spyridon Skordas, et al.
ECTC 2014
Tenko Yamashita, S. Mehta, et al.
VLSI Technology 2015
Arvind Kumar
NANO 2016