Post porosity plasma protection integration at 48 nm pitch
H. Huang, Krystelle Lionti, et al.
IITC/AMC 2016
Line resistance reduction in interconnects was achieved through Cu microstructure modulation. The modulation was performed via both raising annealing temperature and reducing the post-patterning dielectric aspect ratio and resulted in a bamboo-like Cu microstructure. Compared with the conventional polycrystalline, the modulated Cu microstructure also presents a lower resistivity increase rate with area scaling. A TaN stress control layer deposited on over-plated Cu surface was demonstrated to be critical for maintaining the Cu interconnect integrity after the high-temperature anneal.
H. Huang, Krystelle Lionti, et al.
IITC/AMC 2016
Takeshi Nogami, X. Zhang, et al.
VLSI Technology 2017
Chih-Chao Yang, B. Li, et al.
IEEE Electron Device Letters
Fen Chen, Michael Shinosky, et al.
IRPS 2013