Conference paper
Verification of large synthesized designs
D. Brand
ICCAD 1993
A small change in the input to logic synthesis may cause a large change in the output implementation. This is undesirable if a designer has some investment in the old implementation and does not want it perturbed more than necessary. We describe a method that solves this problem by reusing gates from the old implementation, and restricting synthesis to the modified portions only.
D. Brand
ICCAD 1993
A. Devgan, Sandip Kundu
ASP-DAC 1998
Reinaldo A. Bergamaschi, D. Brand, et al.
ICCAD 1995
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