IBM Telum II Microprocessor: 5.5 GHz With On-Die AI and Data Processing, and Design–Technology Co-Optimizations for Power, Area, and Reliability

The IBM Telum II microprocessor features eight cores operating at a base frequency of 5.5 GHz, ten 36-MB L2 caches achieving 3.6-ns access latency, a 360-MB virtual L3 cache, and a new on-chip data processing unit (DPU) for I/O acceleration. As the foundation of the IBM z17 system’s dual-chip modules (DCMs), Telum II maintains high reliability and a power profile within 5% of the prior generation, while simultaneously increasing frequency and increasing latch count by 40%. Power, performance, area, and reliability enhancements span the design stack, including high-density SRAM cells from the Samsung 5-nm technology for increased cache size; design–technology co-optimizations (DTCOs) in the standard cell library image and sequential elements; physical design (PD), logic and architectural advancements to the core and artificial intelligence (AI) accelerator; and improved system-level capacity and encryption.