High Sensitivity Charge Transfer Sense Amplifier

A balanced Charge Transfer sense amplifier for one device cell memory arrays, is presented. Charge transfer techniques are used to preamplify the sense signal and to isolate the large bit/sense (B/S) line capacitance from the nodes of a dynamic latch. The high sensitivity of the sense refresh amplifier is demonstrated in an experimental memory array with a B/S line to cell storage node capacitance ratio of 40 and a sense signal of about 61 mV. Performance limitations are also discussed. Copyright © 1976 by The Institute of Electrical and Electronics Engineers, Inc.