Graphene field-effect transistors with self-aligned gates

We present a device fabrication process that produces graphene-based field-effect transistors with self-aligned gates. This process utilizes the inherent nucleation inhibition of atomic-layer-deposited films with the graphene surface to achieve electrical isolation of the gate electrode from the source/drain electrodes while maintaining electrical access to the graphene channel. Self-alignment produces access lengths of 15-20 nm, which allows for improved device stability, performance, and a minimal normalized contact resistance of 540Ωμm. © 2010 American Institute of Physics.