A 25Gb/s ADC-based serial line receiver in 32nm CMOS SOI
Sergey V. Rylov, Troy Beukema, et al.
ISSCC 2016
We introduce a single-loop PLL that operates in a narrower-bandwidth, integer- mode during phase lock and in a wider-bandwidth, fractional-N mode during transient. This hybrid PLL, as a generalization of the conventional variable-bandwidth PLL that shins only its bandwidth, simultaneously achieves the fast-locking advantage of the fractional-N PLL and design simplicity of the integer-N PLL, and as such, brings benefits in certain important PLL applications. In addition, the frequency division mode switching, unique in the hybrid PLL, enables a new, more digital protocol to execute bandwidth switching. A CMOS IC prototype attests to the validity of the proposed approach. © 2008 IEEE.
Sergey V. Rylov, Troy Beukema, et al.
ISSCC 2016
Nan Sun, Yong Liu, et al.
Solid-State Electronics
Timothy O. Dickson, Yong Liu, et al.
CICC 2015
Byungsub Kim, Yong Liu, et al.
IEEE Journal of Solid-State Circuits