Efficient parallel circuit simulation using bounded-chaotic relaxation

WR-V256, an experimental waveform-relaxation-based parallel circuit simulator for the Victor V256 distributed-memory parallel machine, was used to study performance trade-offs between Gauss-Seidel and bounded-chaotic relaxation algorithms. Several sub-circuit scheduling alternatives within the bounded-chaotic framework were also investigated. We have exercised our simulator on a suite of circuits ranging from 16, 000 to over 93, 000 FETs. Several of the circuits were extracted directly from a 16 Mbit DRAM memory design.