Co capping layers for Cu/low-k interconnects
C.-C. Yang, P. Flaitz, et al.
ADMETA 2010
Grain growth of Cu interconnects in a low-k dielectric was achieved at an elevated anneal temperature of 300 °C without stress-migration-related reliability problems. For this, a TaN metal passivation layer was deposited on the plated Cu overburden surface prior to the thermal annealing process. As compared to the conventional anneal process at 100 °C, the passivation layer enabled further Cu grain growth at the elevated temperature, which then resulted in an increased Cu grain size and improved electromigration resistance in the resulted Cu interconnects. © 2012 IEEE.
C.-C. Yang, P. Flaitz, et al.
ADMETA 2010
A. Deutsch, H. Harrer, et al.
IEDM 1998
L. Clevenger, M. Yoon, et al.
ADMETA 2004
D. Edelstein, R.B. Romney, et al.
Review of Scientific Instruments