Effect of Capping Layer Under Forming Gas Anneal for Back-End-of-Line Oxide Semiconductor FETs

Integrating oxide semiconductor (OS) devices, such as OS-FETs, ferroelectric FETs, OS FET-based gain cells, and scalable memories (e.g., resistive RAMs), into the back-end-of-line (BEOL) have been shown to extend functionality in advanced logic and memory applications [1]-[4]. Previous studies have reported that forming gas annealing (FGA) can significantly enhance device performance, such as increasing remnant polarization in ferroelectric devices and improve the integrity of the gate-stack by passivating dangling bonds in FinFETs [5]-[7]. However, if FGA is performed after OS-FET fabrication in the BEOL, the choice of a protective channel capping layer remains critical, as it influences both the properties and stability of the oxide semiconductor. In this work, we systematically investigate Al2O3, SiO2, and SiN as capping layers, focusing on two key aspects: their interaction with the OS and their stability during FGA. Understanding these effects will aid in selecting the optimal capping layer for OS-FETs, ensuring reliability and performance in BEOL integration.