Designing for a gigahertz

H. Peter Hofstee; Sang H. Dhong; David Meltzer; Kevin J. Nowka; Joel A. Silberman; Jeffrey L. Burns; Stephen D. Posluszny; Osamu Takahashi

doi:10.1109/40.683106

IEEE Micro

Paper

01 May 1998

Designing for a gigahertz

View publication

Abstract

Using a circuit-centric approach, a small team constructed a gigahertz integer processor, more than doubling the frequency of full-fledged designs in the same technology.

Paper

1-GHz fully pipelined 3.7-ns address access time 8 k × 1024 embedded synchronous DRAM macro

Osamu Takahashi, Sang H. Dhong, et al.

IEEE Journal of Solid-State Circuits

Paper

Power-conscious design of the cell processor's synergistic processor element

Osamu Takahashi, Scott Cottier, et al.

IEEE Micro

Paper

Introduction to the cell multiprocessor

James A. Kahle, Michael N. Day, et al.

IBM J. Res. Dev

Conference paper

Verification of delayed-reset domino circuits using ATACS

Wendy Belluomini, Chris J. Myers, et al.

ASYNC 1999

View all publications

Abstract

Related

1-GHz fully pipelined 3.7-ns address access time 8 k × 1024 embedded synchronous DRAM macro

Power-conscious design of the cell processor's synergistic processor element

Introduction to the cell multiprocessor

Verification of delayed-reset domino circuits using ATACS