Circuit Simulation of Nanotechnology Devices with Non-monotonie I-V Characteristics

As research begins to explore potential nanotechnologies for future post-CMOS integrated systems, modeling and simulation environments must be developed that can accommodate the corresponding problem complexity and nontraditional device characteristics. This paper describes a circuit-level simulator that can accommodate an important class of nanotechnology devices that are characterized by nonmonotonic I-V characteristics. Employing adaptively controlled explicit integration method (ACES) and piecewise linear (PWL) device models, the proposed approach effectively overcomes the convergence problems and multiple equilibrium point solution problems caused by the Negative Differential Resistance (NDR) regions in such device I-V functions. Importantly, the ACES approach can address the circuit size problem when partitioning is included, and provide compatibility with simple I-V device model tables, thereby avoiding the need for analytical device models that rarely are available for nanotechnology devices.