Chiplet and Heterogeneous integration Technologies for HPC and AI

High Performance Computing (HPC) systems and AI accelerators, while having different computing characteristics and applications, share a common need for higher performance, improved power efficiency, and flexible scalability. Chiplet and heterogeneous integration are gaining attention in both areas as technologies to meet these requirements. Chiplets optimize and partition functional blocks to manufacture chips, which improves chip yield and enables modularization of designs. On the other hand, heterogeneous integration, which integrates these separate chips in a single package at high density, enables flexible functional configurations by integrating heterogeneous devices and contributes to future system scalability. This presentation will start with the background and focus on the progress of 3D integration, which is the core of heterogeneous integration, and review the process, implementation issues, and experimental results of hybrid bonding technology, which enables higher density and lower power in die-to-die interconnections in particular.