A 27 GHz 20 ps PNP technology
J. Warnock, P.F. Lu, et al.
IEDM 1989
This paper presents a new self-alignment concept for scaled-down bipolar transistors: the self-aligned lateral profile. Using this concept to form the impurity profile and combining it with a wraparound base contact to reduce the emitter-base contact spacing and an n+-polyrefractory metal emitter stack to reduce the emitter resistance, a highperformance and potentially high-yield device structure can be obtained. The device structure can be adapted to a CMOS or merged bipolar-CMOS process and can also be easily optimized for analog applications. Copyright © 1987 by The Institute of Electrical and Electronics Engineers, Inc.
J. Warnock, P.F. Lu, et al.
IEDM 1989
Rajiv V. Joshi, Ching-Te Chuang, et al.
IEEE Transactions on VLSI Systems
J.D. Cressler, D.D. Tang, et al.
ISSCC 1989
C.T. Chuang, G.P. Li, et al.
IEEE T-ED