A scalable, digital BIST circuit for measurement and compensation of static phase offset

An on-chip circuit to measure static phase offset between a reference signal and the feedback signal of a PLL (phase-locked loop) is designed using only digital elements. It is demonstrated in a 65 nm, 1.0 V CMOS technology. It has a measured resolution of 2ps and a range of more than +/- 100ps of phase offset and, and consumes 3mW of power at 1 GHz. It uses an on-chip calibration referred to the reference clock frequency. The measured results are reported through digital scan chains. © 2009 IEEE.