Conference paperA 10b 1.5GS/s pipelined-SAR ADC with background second-stage common-mode regulation and offset calibration in 14nm CMOS FinFETLukas Kull, Danny Luu, et al.ISSCC 2017
Conference paper6.1 A 100Gb/s 1.1pJ/b PAM-4 RX with Dual-Mode 1-Tap PAM-4 / 3-Tap NRZ Speculative DFE in 14nm CMOS FinFETAlessandro Cevrero, Ilter Ozkaya, et al.ISSCC 2019
Conference paperA 40-Gb/s, digitally programmable peaking limiting amplifier with 20-dB differential Gain in 90-nm CMOSJonas R. M. Weiss, Martin L. Schmatz, et al.RFIC 2006
PaperA 22-Gb/s PAM-4 receiver in 90-nm CMOS SOI technologyThomas Toifl, Christian Menolfi, et al.IEEE Journal of Solid-State Circuits
