A 14-nm Energy-Efficient and Reconfigurable Analog Current-Domain In-Memory Compute SRAM Accelerator

This work presents a low-power reconfigurable 12T-SRAM current-domain analog in-memory computing (IMC) SRAM macro design to address non-linearities, process variations, and limited throughput. The proposed design features a time-domain subthreshold multiply and accumulate (MAC) operation with a differential output current sensing technique. Reconfigurable current-controlled design supports different precisions and speeds. A 1kbit macro is prototyped in a 14-nm CMOS process and achieves a measured bitwise energy efficiency of 580 TOPS/W while obtaining highly linear MAC operations. This is the highest energy efficiency reported for IMC current-domain computing methods. In addition, simulation results and estimations based on blocks and 1kb macro measurements show that increasing the macro size to 16kbit can achieve 2128 TOPS/W, which is comparable to other charge domain computing methods. Finally, A fully analog MLP classifier for voice-activity detection (VAD) is prototyped with 3 cascaded analog IMC macros, achieving ~ 90% classification accuracy at 5dB-SNR while consuming 0.58 nJ/classification.