480 MHz 11 mW PR4 Viterbi detector and Margin circuit in 0.25 μm CMOS

This paper describes a Viterbi detector and Margin circuit for PR4 magnetic recording channels. The implementation uses a modified difference-metric formulation of the Viterbi Algorithm (VA). A Viterbi Margin (VM) function is included for channel quality checking purposes. Modifications and implementation techniques that optimize power consumption and speed are described. The VA+VM circuit includes 24+24 bits of path and margin memory, uses 11 mW of power (7 mW for VA alone) at 480 MHz and occupies 0.052 mm2 in a 0.25 μm 1.8 V CMOS process.