1.6 ns access, 1 GHz two-way set-predicted and sum-indexed 64-kByte data cache

Designed to support two cycle execution of load instructions in a 1 GHz single issue, in order, 64-bit reduced instruction set computing (RISC) processor, a 64-kByte, two-way set associative 1.6 ns access, 1 GHz pipelined data cache features up to 16-byte input/output (I/O) to the processor, 128-byte single cycle transfer for reload and cast out operations, and internal forwarding of data for loads that closely follow stores. Cache access is supported by a 512-entry, two-way set associative address translation array and a two read-, one write-port directory that can support bus snoop requests on the second read port.