SparCE: Sparsity Aware General-Purpose Core Extensions to Accelerate Deep Neural NetworksSanchari SenShubham Jainet al.2019IEEE TC
A Compiler for Deep Neural Network Accelerators to Generate Optimized Code for a Wide Range of Data Parameters from a Hand-crafted Computation KernelEri OgawaKazuaki Ishizakiet al.2019COOL CHIPS 2019
Data Subsetting: A Data-Centric Approach to Approximate ComputingYounghoon KimSwagath Venkataramaniet al.2019DATE 2019
A Scalable Multi-TeraOPS Core for AI Training and InferenceSunil ShuklaBruce Fleischeret al.2018IEEE SSC-L
A Scalable Multi-TeraOPS Deep Learning Processor Core for AI Trainina and InferenceBruce FleischerSunil Shuklaet al.2018VLSI Circuits 2018
Compensated-DNN: Energy efficient low-precision deep neural networks by compensating quantization errorsShubham JainSwagath Venkataramaniet al.2018DAC 2018
DyHard-DNN: Even more DNN acceleration with dynamic hardware reconfigurationMateja PuticAlper Buyuktosunogluet al.2018DAC 2018
Exploiting approximate computing for deep learning accelerationChia-Yu ChenJungwook Choiet al.2018DATE 2018
POSTER: Design Space Exploration for Performance Optimization of Deep Neural Networks on Shared Memory AcceleratorsSwagath VenkataramaniJungwook Choiet al.2017PACT 2017
24 Feb 2025US12236338Single Function To Perform Combined Matrix Multiplication And Bias Add Operations
11 Nov 2024US12141513Method To Map Convolutional Layers Of Deep Neural Network On A Plurality Of Processing Elements With Simd Execution Units, Private Memories, And Connected As A 2d Systolic Processor Array
KEKaoutar El MaghraouiPrincipal Research Scientist and Manager, AIU Spyre Model Enablement, AI Hardware Center